Description: 用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted. Platform: |
Size: 9216 |
Author:熊明 |
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Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send. Platform: |
Size: 7168 |
Author:YongZhiLi |
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Description: 可以直接下载到芯片用的带有FIFO的完全UART程序，vhdl语言编写。-Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language. Platform: |
Size: 388096 |
Author:liujingxing |
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Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART. Platform: |
Size: 1106944 |
Author:xiao cao |
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Description: uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code.
Platform: |
Size: 1760256 |
Author:CloudZhang |
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Description: 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC.
This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode.
Data rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput.
For more information see FTDI s appnote "AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf"
Included: VHDL core, NIOS test application, PC test application
Platform: |
Size: 6144 |
Author:李涛 |
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